The present invention is directed to the fabrication of integrated circuits using arrays, gratings, and/or laser interferometry. More particularly, the present invention is directed to a process and methodology of fabricating integrated circuits that accounts for both optical proximity and spatial frequency effects while maintaining the resolution-enhancement characteristics required by sub-wavelength lithography.
Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc) has been built up around this technology.
In this process, a mask, or xe2x80x9creticlexe2x80x9d, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics/lenses that project light coming through the reticle and image the circuit pattern, typically with a 4xc3x97 to 5xc3x97 reduction factor, on a photo-resist film formed on a silicon wafer. The term chrome refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
FIG. 1 is an example of a conventional optical projection lithography apparatus. As illustrated in FIG. 1, the optical projection lithography apparatus includes a light source 20, a photomask 22, and reduction optics 24. A wafer 26, having a layer of photo-resist 28 thereon, is placed within the optical projection lithography apparatus, and the light-source 20 generates a beam of light 21 that is incident upon the photomask 22. The reduction optics 24 reduces the light beam to cause a pattern 30 that exposes the photo-resist layer 28, creating the pattern 30 of reacted material in the resist layer 28. In this manner, a pattern 32, provided on the mask 22, is transferred to the photo-resist layer 28 on the wafer 26.
The photo-resist pattern 30 is then transferred to the underlying wafer 26 through standard etching processes using standard semiconductor fabrication techniques. Both positive and negative tone resists can be used to produce either positive or negative images of the mask pattern on the wafer.
As the semiconductor industry continues to evolve and grow, feature sizes of the pattern are driven to an ever-smaller resolution. The driving force is the desire of these industries to remain on the xe2x80x9cMoore""s Lawxe2x80x9d growth curve. The xe2x80x9cMoore""s Lawxe2x80x9d growth curve calls for an exponential increase of circuit density versus production year that is typically accomplished by decreasing feature sizes. However, the resolution of an optical stepper is limited by the wavelength of the light source, and is further limited by the numerical aperture (xe2x80x9cNAxe2x80x9d) of the lens.
The basic lithographic imaging relationships are:
1) Resolution=k1/NA; and
2) Depth of Focus=k2/(NA)2;
where is the illumination wavelength, NA is the lens numerical aperture, and k1 and k2 are process constants.
In general, a shorter wavelength light source and/or a higher numerical aperture lens affords a higher-resolution system. State-of-the-art light sources provide a beam having a wavelength of approximately 193 nanometers. As stated above, the semiconductor industry has been driving the need for critical feature sizes to decrease exponentially over time while exposure light sources have only been decreasing linearly with time.
Carrying this scenario forward, current and future optical lithography will be required to image feature sizes of sub-wavelength dimensions. Sub-wavelength optical lithography has been realized with the 180-nm device generation fabricated using 248-nm optical lithography.
As noted above, the numerical aperture of the lens also drives resolution. In this field, the cost of lenses having very high numerical apertures (xe2x80x9cNAxe2x80x9d) approaching 0.8 is very high. Moreover, linear NA increases are not sufficient to maintain pace with the need for exponentially decreasing feature sizes.
To meet this demand, Resolution-Enhanced optical lithography Technologies (xe2x80x9cRETxe2x80x9d) have become popular as techniques for providing patterns with sub-wavelength resolution. These methods include off-axis illumination (xe2x80x9cOAIxe2x80x9d), optical proximity correction (xe2x80x9cOPCxe2x80x9d), and phase-shift masks (xe2x80x9cPSMsxe2x80x9d). Such resolution-enhanced optical lithography methods are especially useful for generating physical devices on a wafer that require small size and tight design tolerance. Examples of such physical devices are the gate length of a transistor or the dimensions of contact cuts formed in inter-layer dielectrics. However, the conventional RET methods face problems with layout complexity and data size, mask fabrication complexity and resulting cost, and optical proximity effects (CUT effects) and spatial frequency effects which are discussed below.
In many circuit applications, it is an important design constraint that the respective sizes of the narrow lines are consistent throughout the circuit. For example, in a semiconductor device, the narrow lines may form transistor gates, and it is important that the transistor gates are similar in size so that the circuit has consistent and predictable gate delay values.
In general, in any optical lithography technique, the resulting optical image intensity is a function of the proximity of features. Contrast is lost as feature pitch values decrease. As a result, the resulting size of features located in densely populated regions can be different than the size for those features that are isolated from the densely populated features. This is known as the xe2x80x9coptical proximityxe2x80x9d effect.
With respect to optical proximity effect, the critical dimension of features depends on feature density. Moreover, optical proximity effects can become more severe in sub-wavelength lithography. The optical proximity effects can result in dense lines 261 and isolated line 262 on wafer 26 being printed with different sizes, even if the same size on the mask, as illustrated in FIG. 2, or dense contacts 263 and isolated contact 264 on wafer 26 being printed with different sizes, even if the same size on the mask, as illustrated in FIG. 3. Since the performance of the circuit depends on the size and size tolerance of the gates, this is an undesirable result.
Spatial frequency effects are caused by the xe2x80x9clow-pass filterxe2x80x9d behavior of a projection lithography lens wherein high spatial frequencies do not pass through the lens. This results in corner rounding and line end shortening. An example of this effect is illustrated in FIG. 4. As illustrated in FIG. 4, a desired image is represented by mask 220, but the actual image pattern 265 on the wafer is shortened and rounded.
To compensate for optical proximity and spatial frequency effects, additional features have been conventionally introduced on the mask that can involve both printable as well as sub-resolution elements. In these methods, extra features such as serifs, mousebites, hammerheads, and scattering bars are added to the mask features in order to correct for optical proximity effects and other spatial frequency effects. These conventional methods involve sophisticated algorithms with very large data size, as different corrections are required for each separation distance between the features. For this reason, conventional feature size correction (xe2x80x9cOPCxe2x80x9d or optical proximity correction) is a costly and time-consuming process.
Conventional OPC generally involves the processing of an enormous data volume. The hierarchical data processing algorithms used for conventional circuit design are of limited utility because optical proximity effects are based on the nature of geometries surrounding a particular circuit element. For example, a 1xc3x97 AND gate surrounded by registers on all sides will perform differently than a 1xc3x97 AND gate surrounded by other 1xc3x97 AND gates. Other examples of conventional lithography methods addressing the need for finer features or higher-resolution features will be discussed below.
U.S. Pat. No. 5,415,835-B1 (xe2x80x9cBrueck et al.xe2x80x9d) discusses a method of fine-line imaging based on laser interferometry. In Brueck et al., dense gratings formed by laser interferometry are customized by additional exposures using both interferometric and conventional lithography. Brueck et al. does not address optical proximity and spatial frequency effect problems thus limiting the ultimate density and flexibility of the patterns produced. In addition, the multiple exposures are not substantially independent in the optical sense due to the resist""s xe2x80x9cmemoryxe2x80x9d of previous exposure patterns. It is also difficult to make an arbitrary two-dimensional pattern in this way.
EP-0915384-A2 (xe2x80x9cSuzuki et al.xe2x80x9d) expands upon interferometric lithography. Suzuki et al. discloses using interferometric one-dimensional gratings to realize fine-line lithography together with subsequent customization exposures using multiplex (subthreshold) exposure doses. Suzuki et al. does not address optical proximity and spatial frequency effect problems thus limiting the ultimate density and flexibility of the patterns produced. The multiple exposures are not substantially optically independent due to the resist""s xe2x80x9cmemoryxe2x80x9d of the previous exposures. It is also difficult to realize an arbitrary 2D pattern with this method. Since the fine features are only realized in one orientation, it is difficult to form patterns with fine features in both the x and y directions.
WO-1/06320-A1 (xe2x80x9cLevensonxe2x80x9d) discloses re-usable xe2x80x9cmasterxe2x80x9d fine feature phase-shift masks that can be customized by multiple exposure methods using conventional masks. Levenson discloses a xe2x80x9ctrade-off between a maximum density of features against the cost for low volume runsxe2x80x9d. Thus, the target application is primarily ASIC and thin-film head patterns where the pattern density is not too great. Just as in the previous Patents discussed above, this method does not mitigate optical proximity and spatial frequency effects. It does not include substantially independent multiple exposures.
Finally, U.S. Pat. No. 6,184,151-B1 (xe2x80x9cAdair et al.xe2x80x9d) discloses a method for forming square shape images wherein a first plurality of lines running in a first direction is defined in a first layer, and then a second resist is defined wherein the lines run in an intersecting pattern to those of the first layer, thereby creating sharp corners wherever the first and second layers intersect and in open areas between the lines. This process addresses the spatial frequency effect problems of corner rounding and line-end shortening, but does not resolve the optical proximity effect problem. The control of fine features through pitch is important in order to realize the maximum pattern density and flexibility for applications.
It is therefore desirable to develop an imaging method that mitigates optical proximity and spatial frequency effects without adding complex optical proximity correction features to the mask, while preserving the resolution enhancement aspects required by sub-wavelength lithography. This is especially desirable since conventional optical proximity correction approaches are becoming quite difficult to implement as imaging requirements continue to move deeper into the sub-wavelength regime.
It is also desirable to eliminate basic optical proximity effects, involving the imaging of fine lines in the x and y directions through a variety of pitch values and to minimize spatial frequency effects such as corner rounding and line-end shortening by the use of multiple, xe2x80x9csubstantially independentxe2x80x9d optical exposures. The phrase, xe2x80x9csubstantially independent imaging,xe2x80x9d means that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions.
It is further desirable to simplify circuit layout and mask fabrication, resulting in lower cost and substantially decreased data volume required for a typical design, thereby allowing for design of standard cells that can be accurately characterized independently of their eventual placement in a larger circuit.
One aspect of the present invention is a method of forming patterns on a substrate. The method exposes the substrate to provide a pattern of dense features and exposes the substrate to provide multiple trimmed patterns on the substrate, the trimmed patterns including both densely populated and sparsely populated regions of features, the critical dimension of the features in the densely populated regions and sparsely populated regions being substantially independent of feature density.
Another aspect of the present invention is a mask set for a process for providing patterns on a substrate. The mask set includes a fine feature mask containing a pattern of dense features and a trim mask for producing multiple trimmed patterns of fine features.
A third aspect of the present invention is a design method. The design method designs standard circuit subcell designs wherein all fine features lie on a regular pattern. The designing of the standard circuit subcell designs is compatible with a method of forming patterns on a substrate by exposing the substrate to provide a pattern of dense features and exposing the substrate to provide multiple trimmed patterns on the substrate, the trimmed patterns including both densely populated and sparsely populated regions of features, the critical dimension of the features in the densely populated regions and sparsely populated regions being substantially independent of feature density.
A fourth aspect of the present invention is a design method. The design method designs standard circuit subcell designs wherein all fine features lie on a regular pattern. The designing of the standard circuit subcell designs is compatible with a mask set for providing patterns on a substrate having a fine feature mask containing a pattern of dense features and a trim mask for producing multiple trimmed patterns of fine features.
A fifth aspect of the present invention is a computer-aided design methodology. The computer-aided design methodology assumes a first template of dense-only features as a first mask level and places a first set of trim features on a second mask level to coincide with selected features on the first template, such that a first subset or superset of features desired for fabrication correspond to a geometric function of the first template and the first set of trim features.
A sixth aspect of the present invention is a design methodology. The design methodology assumes a first template of dense-only features as a first mask level and places a first set of trim features on a second mask level to coincide with selected features on the first template, such that a first subset or superset of features desired for fabrication correspond to a geometric function of the first template and the first set of trim features.
A seventh aspect of the present invention is a method of forming a random contact array on a substrate. The method exposes the substrate to provide a pattern of dense contact features of a predetermined pitch and critical dimension and exposes the substrate to provide multiple trimmed patterns on the substrate, the trimmed patterns including both densely populated and sparsely populated regions of features, the critical dimension of the features in the densely populated regions and sparsely populated regions being substantially independent of feature density.
An eighth aspect of the present invention is a method for defining multiple fine feature critical dimensions in a resist for a single feature definition exposure. The method exposes a substrate with a feature definition exposure and sub-threshold exposes the substrate using a gray-tone mask to locally partially expose different regions of the substrate, thereby allowing for a range of critical dimensions to be defined by the feature definition exposure.